There is now an increasing interest in the semiconductor industry in high speed memory devices such as a random access memory device with page mode operation or with nibble mode operation. The random access memory device is accessible in page mode operation with successive column address signals under a specified single row address. Namely, when a row address is supplied to the random access memory device, a single row of memory cells is selected for access. Then, column address signals are supplied to the random access memory to specify the memory cells in the selected row of the memory cells. When one of the memory cells is specified by the column address signal, a data bit is read out from the specified memory cell and the data bit is supplied to a sense amplifier circuit for decision of the logic level, then amplifying and placing in an output buffer circuit for transferring to a destination. This means that a time period necessary to access a data bit in the page mode operation is approximately equal to the total of the time periods for decision of the column address, turning on the switching transistor between the column line pair and the data lines, activation of the sense amplifier circuit, amplification and placing in the output buffer circuit. In other words, a data bit is accessible in the page mode operation in a time period without consideration of the row address signal. This results in shrinkage in access time.
Similarly, the nibble mode operation is useful for reduction in access time. In a nibble mode operation, accessible memory cells are limited to four. The first memory cell is specified by the row and column address signals latched in synchronous with the row address strobe signal and the column address signal, respectively. However, the remaining three memory cells are accessible in a predetermined order with applications of the column address strobe signals only. This results in high speed read out operation. In order to realize the high speed nibble mode operation, it is necessary to activate four memory cells having addresses strongly related to one another. For example, the second memory cell may be assigned an address specified by a row address signal identical with the row address signal for the first memory cell and by a column address signal only different in logic level of the most significant bit from that for the first memory cell. In a similar manner, the third memory cell may be assigned an address specified by a row address signal only different in the logic level of the most significant bit from that for the first memory cell and by a column address signal identical with that for the first memory cell. However, the fourth memory cell may have an address specified by a row address signal and a column address signal each only different in the logic level of the most significant bit from that for the first memory cell. When the first memory cell is accessed, the remaining three memory cells are simultaneously activated and the logic level of each data bit preserved therein is determined by the sense amplifier circuit. Then, the data bits are successively read out by toggle operations using the column address strobe signals. In order to realize the toggle operation, the random access memory device is usually provided with a nibble decoder circuit which serves as four-to-one decoder circuit, and the output buffer circuit successively transfers the data bits from the nibble decoder circuit to the destination.
Referring to FIG. 1 of the drawings, a typical example of the random access memory device with the nibble decoder circuit is illustrated. In a read-out operation, an address buffer/inverter circuit 1 allows row and column address decoder circuits to activate four memory cells each selected from each memory cell array 2, 3, 4 or 5, then data bits preserved therein are read out and transferred to respective sense amplifier circuits 6, 7, 8 and 9. The sense amplifier circuits 6, 7, 8 and 9 decide the logic levels of the data bits read out from the four memory cells, respectively, and the four data bits are transferred through respective "Y" switch circuits to read/write switch circuits 10, 11, 12 and 13. A mode selecting signal R/W has been supplied from a timing generator circuit (not shown) to read/write control circuits 14 and 15, so that the read-out switches of the read/write switch circuits 10, 11, 12 and 13 are turned on to transfer the data bits to the data amplifier circuits 16, 17, 18 and 19, respectively. The address buffer/inverter circuit 1 supplies the most significant bits of the row and column address signals and the inverses thereof to nibble decoder circuit 21, so that the nibble decoder circuit 21 allows nibble switching transistors 22, 23, 24 and 25 to successively turn on in synchronous with the column address strobe signals. Then, the four data bits successively pass through the respective nibble switching transistors 22, 23, 24 and 25 and are supplied in succession to the output buffer circuit 26 for serial read-out or nibble mode operation.
On the other hand, when the random access memory device is shifted to the write-in operation in response to the mode selecting signal R/W, the address buffer/inverter circuit 1 allows the row address decoder circuits and the column address decoder circuits to select four memory cells from the memory cell arrays 2, 3, 4 and 5, respectively. A new data bit is supplied from the outside thereof to an input buffer circuit 27, and the nibble decoder circuit 21 allows one of the nibble switching transistors 22, 23, 24 and 25 to turn on based on the most significant bits of the row and column address signals. Then, one of the nibble switching transistors 22, 23, 24 and 25 turns on to transfer the new data bit to the data amplifier circuit 16, 17, 18 or 19. The read/write control circuit 14 and 15 has already selected the write amplifier circuits and the write switches of the read/write switch circuits 10, 11, 12 and 13 on the basis of the mode selecting signal R/W, however the nibble decoder circuit 21 allows only one of the write amplifier circuits accompanied by the selected nibble switching transistor and the write switch associated with the write amplifier circuit on the basis of the most significant bits of the row and column address signals. In this device, the read/write control circuits 14 and 15 are activated upon a write-in operation and a read-out operation, respectively. Then, the new data bit is transferred to the selected write switch and supplied through the "Y" switch circuit to one of the memory cell arrays 2, 3, 4 and 5. This means that the remaining three data amplifier circuits are kept in respective inactive states for preventing the data bits preserved in the unselected memory cells from destruction. Thus, the prior-art random access memory device is expected to have the nibble decoder circuit 21 capable of controlling not only the nibble switching transistors 22 to 25 but also the read/write switch circuits 10 to 13 each accompanied by the data amplifier circuit, and, for this reason, another random access memory device employs a nibble decoder circuit combined with the read/write control circuit. FIG. 2 shows the circuit arrangement of such a random access memory device, and circuits and arrays are respectively denoted by reference numerals used for designating the corresponding circuits and arrays of the random access memory device illustrated in FIG. 1, so that detailed description will be omitted for the sake of simplicity.
However, a problem is encountered in the prior-art random access memory device shown in FIG. 1 in controllability in the write-in mode operation. Namely, the read/write control circuits 14 and 15 controls the read/write switch circuits each accompanied by the data amplifier circuit, and the nibble decoder circuit 21 is expected to control the read/write switch circuits and the data amplifier circuits as well as the nibble switching transistors independent from the read/write control circuits. This results in complicate control or deterioration in controllability.
On the other hand, the prior-art random access memory device shown in FIG. 2 has the nibble decoder circuit 28 combined with the read/write control circuit so that the random access memory device is free from the complicate control but has drawbacks in complicate circuit arrangement of the combined nibble decoder circuit. This results in deterioration in operation speed because of the fact that the combined nibble decoder circuit needs to make all decisions at all times.
Prior art random access memory devices are disclosed by S. Sheffield et al. in "A 100 ns 64K Dynamic RAM using Redundancy Techniques" in the Digest of Technical Papers, ISSCC 81, pages 84 and 85, and by Hiroaki Ikeda in Japanese Patent Application No. 57-187702. However, the nibble decoder circuits of these random access memory devices need to supply decoded control signals to the read/write switch circuits, so that the circuit complexities still remain in the prior-art random access memory devices disclosed in the above documents.